0:01:10.810,0:01:18.100 In this last part in our series of lectures[br]on computer organization, let us take a look 0:01:18.100,0:01:20.380 at the bus. 0:01:20.380,0:01:22.329 What is a bus? 0:01:22.329,0:01:31.399 So far we had seen the blocks of CPU, memory,[br]I/O and the interconnecting bus. 0:01:31.399,0:01:37.679 On more than one occasion, I had pointed out[br]that we have to evolve some kind of standardization 0:01:37.679,0:01:46.070 so that the system from the bus we will see[br]something uniform because you may be having 0:01:46.070,0:01:51.030 different types of memory systems and you[br]may be having different types of devices but 0:01:51.030,0:01:55.159 the CPU must see something uniform on the[br]bus on the bus end. 0:01:55.159,0:02:02.180 In spite of all these, though we talk about[br]standards, we would find that there are different 0:02:02.180,0:02:09.389 standards; obviously because the CPU and memory[br]work at some rate different from I/O. 0:02:09.389,0:02:15.730 If at all CPU is directly involved, that is[br]going to be at another rate; then, memory 0:02:15.730,0:02:24.109 I/O will be a different rate; and in I/O,[br]you have a spectrum from the lowest K speed 0:02:24.109,0:02:26.440 to the fastest one. 0:02:26.440,0:02:36.690 So generally, we would find that there are[br]different types of buses and when a processor 0:02:36.690,0:02:43.799 comes with some brand name in the market,[br]you would find that that particular manufacturer 0:02:43.799,0:02:46.340 comes out with its own bus also. 0:02:46.340,0:02:56.160 By the time that particular bus gets standardized,[br]you would find that the bus is no longer very 0:02:56.160,0:03:01.710 relevant, mainly because the processor is[br]outdated. 0:03:01.710,0:03:10.200 Nevertheless, we can always talk in the case[br]of bus; in general, about the specifications 0:03:10.200,0:03:15.560 of the bus. 0:03:15.560,0:03:22.360 Here there are certain things which you may[br]find are common and there are certain things 0:03:22.360,0:03:26.080 which would keep varying. 0:03:26.080,0:03:32.170 Now while specifying a bus, what exactly is[br]the bus; what is it we have talked about earlier? 0:03:32.170,0:03:36.569 We have always said a bus is a set of signal[br]lines. 0:03:36.569,0:04:00.920 We had introduced the bus as a set of signal[br]lines. 0:04:00.920,0:04:10.690 Bus in fact is a term introduced by Americans;[br]earlier the British used to call it highway. 0:04:10.690,0:04:17.750 Now that particular term is coming in a different[br]context like super highway for information 0:04:17.750,0:04:18.750 and so on. 0:04:18.750,0:04:22.660 Earlier they were calling it highway. 0:04:22.660,0:04:29.400 Essentially on a highway something moves;[br]but Americans used the bus. 0:04:29.400,0:04:35.030 Now in the case of computer system, we can[br]say the bus is like a highway over which the 0:04:35.030,0:04:36.530 data moves – there is some communication. 0:04:36.530,0:04:51.120 But Americans called it bus – since bus[br]is a set of signal lines, these signal lines 0:04:51.120,0:04:57.120 are carried over lines, which form conductors. 0:04:57.120,0:05:09.520 So the bus has conductors and a bus is usually[br]long; while trying to meet an electrical specification, 0:05:09.520,0:05:20.190 you will find that you would need some current[br]amplifiers, we call them current drivers. 0:05:20.190,0:05:27.180 That means along with the bus or as part of[br]a bus, you have drivers. 0:05:27.180,0:05:31.870 So you can see that a bus has drivers and[br]conductors and we are quite familiar with 0:05:31.870,0:05:34.000 the term bus. 0:05:34.000,0:05:43.680 Now let us go into certain aspects of the[br]specifications. 0:05:43.680,0:05:51.400 There are actually three types of specifications[br]but usually in computer organization, or we 0:05:51.400,0:05:55.889 may say even computer scientists will be concerned[br]more with only one thing. 0:05:55.889,0:06:00.729 That particular thing is called the logical[br]specification of the bus. 0:06:00.729,0:06:07.300 In fact all the time when we were talking[br]about some transfer over the bus, we were 0:06:07.300,0:06:10.229 indicating this. 0:06:10.229,0:06:11.759 What is it we said earlier? 0:06:11.759,0:06:19.550 We said the CPU places address on the bus[br]and if it were a read cycle, the CPU also 0:06:19.550,0:06:27.150 places a read signal on the bus, and then[br]the memory responds with data and it puts 0:06:27.150,0:06:28.250 it on the bus. 0:06:28.250,0:06:31.530 CPU, of course, reads it in. 0:06:31.530,0:06:38.789 So you can see that there is generation of[br]address, signal generation of read signal 0:06:38.789,0:06:41.870 and strobing the data that’s available. 0:06:41.870,0:06:44.300 This is what we were talking about all the[br]time. 0:06:44.300,0:06:45.410 Now what is the data? 0:06:45.410,0:06:49.699 Data is a pattern of 1s and 0s; it is a string[br]of 1s and 0s. 0:06:49.699,0:06:52.720 Similarly address also is a string. 0:06:52.720,0:06:57.889 So all the time we were only talking about[br]the logical aspect of it because we never 0:06:57.889,0:07:07.190 said the data which is 1 means say 1 volt;[br]0 means say 0 volts or any such thing; we 0:07:07.190,0:07:11.539 did not talk about any physical, real-world[br]quantity. 0:07:11.539,0:07:14.710 We were not referring to any physical quantity. 0:07:14.710,0:07:18.220 We are talking about a read as a read signal,[br]write as a write signal. 0:07:18.220,0:07:22.910 We never said read means what must be the[br]voltage and so on and so forth. 0:07:22.910,0:07:27.569 So that is what we are talking about when[br]we talk about the logical specification; another 0:07:27.569,0:07:37.110 thing as you would have noticed is that we[br]are talking about sequence of actions. 0:07:37.110,0:07:44.750 What are the things we were mentioning? 0:07:44.750,0:07:57.080 We said first address, then read and then[br]the data comes, which is strobed, so we were 0:07:57.080,0:07:58.449 talking about sequence also. 0:07:58.449,0:08:07.409 In other words, the sequence of actions which[br]is part of what we refer to as bus protocol, 0:08:07.409,0:08:14.080 is only one specific way in which this read[br]or write can be performed. 0:08:14.080,0:08:23.860 So we talk about logical signals involved[br]and then we also talk about the sequence in 0:08:23.860,0:08:27.720 which the signals must be generated. 0:08:27.720,0:08:34.260 Now generally when we discuss the bus in computer[br]science, or from a computer scientist’s 0:08:34.260,0:08:38.909 point of view, we will always be concerned[br]with these logical aspects. 0:08:38.909,0:08:45.920 But later as I was just trying to point out,[br]there are two things: one is the electrical 0:08:45.920,0:08:48.140 specification. 0:08:48.140,0:08:55.480 So when we talk about the electrical specification[br]of the bus, I have to say for instance what 0:08:55.480,0:08:57.699 does 1 mean? 0:08:57.699,0:09:11.480 Do 1 and 0 there refer to say some voltage[br]signals or current signals or some other signals? 0:09:11.480,0:09:20.900 And if for instance 1 and 0 will be represented[br]by plus 5 V and 0 V or 3 V, plus 3 V and plus 0:09:20.900,0:09:29.130 0.2 V or let us say plus 15 V and minus 15[br]V. 0:09:29.130,0:09:33.400 All these things really refer to the physical[br]quantities. 0:09:33.400,0:09:38.530 They would come into the electrical specification[br]of the bus. 0:09:38.530,0:09:44.690 It is not enough if we say that the address[br]is placed. 0:09:44.690,0:10:00.519 We have to specify exactly what must be the[br]levels of the voltage or current signals. 0:10:00.519,0:10:13.700 Essentially we can just put it as physical[br]specification, but then the mechanical specification 0:10:13.700,0:10:16.030 of the bus also has to be specified. 0:10:16.030,0:10:23.870 So together, these two form the physical part[br]of the bus and this forms the logical part 0:10:23.870,0:10:26.540 of the bus. 0:10:26.540,0:10:33.040 One talks about the electrical signal levels[br]and so on, the other one talks about the mechanical 0:10:33.040,0:10:34.170 thing. 0:10:34.170,0:10:44.329 So this would say how long the bus conductor[br]can be and what sort of edge connector is 0:10:44.329,0:10:50.959 used – is it something like 32 pin or 62[br]pin and if it is this pin, is it a parallel 0:10:50.959,0:10:55.160 or are the pins parallel or staggered, etc. 0:10:55.160,0:11:03.089 For instance, if we talk about the standard[br]bus, we have specification along all the three 0:11:03.089,0:11:04.089 dimensions. 0:11:04.089,0:11:12.360 If we say multi-bus, there is a specific multi-bus[br]connector and each of the multi-bus signals 0:11:12.360,0:11:20.220 is going to be defined in terms of some electrical[br]voltage current and so on. 0:11:20.220,0:11:23.700 And then we also talk about this particular[br]one. 0:11:23.700,0:11:26.120 So essentially we will only concentrate on[br]this. 0:11:26.120,0:11:31.670 But let us not forget that there are these[br]specifications also; somebody must concern 0:11:31.670,0:11:33.850 with this; otherwise there is no standard. 0:11:33.850,0:11:37.250 Now why must we be concerned even down to[br]the level of mechanical? 0:11:37.250,0:11:42.540 That is mainly because this is the one which[br]is going to give freedom to the user. 0:11:42.540,0:11:49.089 So if we say use multi-bus one connector or[br]multi-bus two connectors or some other X bus, 0:11:49.089,0:11:55.350 new bus, and then all he does is he goes to[br]the shop and ask for that connector and then 0:11:55.350,0:11:59.740 brings it and then machine properly without[br]any difficulty. 0:11:59.740,0:12:05.000 He is not going to be bothered about either[br]logical aspect or electrical aspect; for him, 0:12:05.000,0:12:11.209 when he keys in, there must be a display and[br]that particular display must mean something 0:12:11.209,0:12:14.270 to him at a higher level. 0:12:14.270,0:12:20.050 Having said that, we will be concentrating[br]on the logical aspects of this bus. 0:12:20.050,0:12:24.170 We can note that essentially there are again[br]three sections. 0:12:24.170,0:12:30.640 The first one we may say is concerned with[br]the data transfer. 0:12:30.640,0:12:34.250 This is the one we keep talking all that time[br]about. 0:12:34.250,0:12:41.320 That is, we say that the CPU places address,[br]indicates what type of transfer, read or write, 0:12:41.320,0:12:48.010 input or output, whatever it wants, and then[br]memory or I/O responds. 0:12:48.010,0:12:53.760 So all these things: placing the address,[br]placing the appropriate control signal, and 0:12:53.760,0:12:57.800 then passing on the data will come under the[br]data transfer aspect. 0:12:57.800,0:13:04.810 Now as the CPU is involved in this data transfer[br]because what is going on in any instruction 0:13:04.810,0:13:11.060 cycle again and again is the same thing, fetching[br]an instruction, interpreting, executing, as 0:13:11.060,0:13:17.010 part of executing fetching a data, that is,[br]instruction or data fetching – it all comes 0:13:17.010,0:13:18.010 under the data transfer. 0:13:18.010,0:13:20.720 This is what is going on in every instruction[br]cycle. 0:13:20.720,0:13:27.899 Now this is the essential thing as far as[br]the processor is concerned. 0:13:27.899,0:13:33.730 As this goes on some other device may indicate[br]that it is ready; in the case of interrupt, 0:13:33.730,0:13:35.589 is it not. 0:13:35.589,0:13:42.420 Now in a system which has n number of devices,[br]that is, multiple devices, we also said that 0:13:42.420,0:13:48.339 we have to look in to the priority among these[br]when there is a multiple request for this 0:13:48.339,0:13:49.829 CPU attention. 0:13:49.829,0:13:57.850 So we have to basically see that there is[br]priority checking and so on. 0:13:57.850,0:14:05.589 We may put this particular one as priority[br]arbitration; meaning as CPU is busy with the 0:14:05.589,0:14:22.130 transfer, then possibly there is some other[br]specialized hardware unit, which looks into 0:14:22.130,0:14:24.620 the action. 0:14:24.620,0:14:31.399 Priority arbitration can go on in parallel[br]with the data transfer. 0:14:31.399,0:14:43.880 For instance as part of the some instruction[br]cycle, when one of the n devices or two of 0:14:43.880,0:14:50.790 the devices indicate that readiness, then[br]there is a conflict. 0:14:50.790,0:14:58.019 Now the priority arbitrator will look in to[br]the requests and then will choose the higher 0:14:58.019,0:15:05.329 priority device between those two so that[br]when the instruction cycle is complete it 0:15:05.329,0:15:09.769 can go ahead, that is, in the case of interrupt. 0:15:09.769,0:15:17.200 So priority arbitration is another piece of[br]action that goes on and we will have dedicated 0:15:17.200,0:15:29.310 signal lines as part of the bus because then[br]only two things can go on in parallel; otherwise 0:15:29.310,0:15:30.690 it is not possible. 0:15:30.690,0:15:36.940 If the same sets of signal lines are going[br]to be used, one has to keep idling. 0:15:36.940,0:15:43.199 For instance that was the situation in the[br]case of DMA. 0:15:43.199,0:15:50.550 The I/O is directly accessing the memory so[br]CPU is going out of action. 0:15:50.550,0:16:02.440 The third aspect of this bus we may just put[br]in general as initialization. 0:16:02.440,0:16:04.649 Different people may call it differently. 0:16:04.649,0:16:11.399 What exactly we mean here is something to[br]do with checking about the power, the system 0:16:11.399,0:16:21.089 clock, and few other signal lines, which really[br]not take direct part in data transfer or priority 0:16:21.089,0:16:22.089 arbitration. 0:16:22.089,0:16:23.990 There will be another set of signal lines. 0:16:23.990,0:16:28.750 We may just call them for instance system[br]reset signal. 0:16:28.750,0:16:36.280 So that can come under the initialization[br]and a few other things: system clock, system 0:16:36.280,0:16:43.850 reset, some special signal lines, monitoring[br]the power – all these things will come under 0:16:43.850,0:16:46.959 this. 0:16:46.959,0:16:52.259 So we as we talk about the data transfer;[br]we should also take a look at what is going 0:16:52.259,0:16:58.180 on in this and also know the functions of[br]some of these because there is no standard 0:16:58.180,0:17:00.480 about this particular thing. 0:17:00.480,0:17:06.520 So generally when you study any bus, you may[br]be able to identify a group of signals belonging 0:17:06.520,0:17:12.760 to this or this or this category. 0:17:12.760,0:17:19.290 Now there are different types of buses, we[br]may say. 0:17:19.290,0:17:24.780 Actually I am not talking about just the standard[br]buses here. 0:17:24.780,0:17:34.419 I am just trying to give what you may call[br]a generic or general classification. 0:17:34.419,0:17:35.950 What are the various things involved? 0:17:35.950,0:17:42.610 For instance, we are not talking about multi-bus[br]or a new bus or uni-bus or a mass bus and 0:17:42.610,0:17:45.909 so on; we are discussing purely from functional[br]point of view. 0:17:45.909,0:17:56.169 Now we know that CPU and memory, both work[br]at electronic speed. 0:17:56.169,0:18:12.350 So it is meaningful to have a processor memory[br]bus and have it somewhat different, distinct 0:18:12.350,0:18:22.849 from what you may call the second one as an[br]I/O bus mainly because in the case of processor 0:18:22.849,0:18:30.750 memory, the transfer is going to be very fast[br]whereas in the case of I/O bus, we do not 0:18:30.750,0:18:31.750 know. 0:18:31.750,0:18:39.150 We have devices with varying speeds, characteristics,[br]and what not. 0:18:39.150,0:18:47.390 Then there is another bus also that we talk[br]about; that is generally called a back plane 0:18:47.390,0:18:49.090 bus. 0:18:49.090,0:18:56.920 In some systems we may not able to identify[br]them separately. 0:18:56.920,0:19:02.420 For instance the processor of the memory bus[br]itself may act as a back plate bus; it is 0:19:02.420,0:19:08.280 not necessary that all the three must exist[br]in all the systems. 0:19:08.280,0:19:15.669 Now let us say some one is looking up the[br]system with an Intel processor. 0:19:15.669,0:19:24.470 Then suited with that particular Intel processor,[br]there may be certain memory chips. 0:19:24.470,0:19:32.879 It is even possible that the manufacturer[br]of the processor or the CPU has also come 0:19:32.879,0:19:40.560 up with a set of memory chips, which would[br]directly talk in the sense there will be some 0:19:40.560,0:19:42.450 special features about that memory. 0:19:42.450,0:19:50.050 For instance let us say suppose you have a[br]processor with multiplexed bus, there is let 0:19:50.050,0:19:52.770 us say address and data multiplex. 0:19:52.770,0:20:00.000 If you have the memory chips or the memory[br]controller, which goes with the chip in the 0:20:00.000,0:20:07.179 memory bus system, it can take care of the[br]multiplexing, so that internally it buffers 0:20:07.179,0:20:09.419 and then de-multiplexes that. 0:20:09.419,0:20:18.400 Then it is meaningful; and so what happens[br]is this processor memory bus essentially we 0:20:18.400,0:20:30.560 may say is a short bus and also it is a bus[br]which does transaction as fast as possible. 0:20:30.560,0:20:41.899 We can understand fast because, for this processor[br]utilization to be the highest, maximal, it 0:20:41.899,0:20:52.790 must be fast and invariably the processor,[br]memory, and the bus are interconnecting the 0:20:52.790,0:20:55.340 processor memory bus on a single board itself. 0:20:55.340,0:21:04.230 That is why invariably we define that particular[br]thing as a short bus and there may not be 0:21:04.230,0:21:06.030 any standard about this also. 0:21:06.030,0:21:11.340 For an Intel processor, there may be a set[br]of things; for a Motorola processor there 0:21:11.340,0:21:12.530 may be another set of things. 0:21:12.530,0:21:21.720 It is all because of the signals that are[br]generated by the respective processor. 0:21:21.720,0:21:28.890 We can say that this processor memory bus[br]is a proprietary bus because we have a specific 0:21:28.890,0:21:35.470 processor and then we have specific memory[br]requirement; it is not open for the general 0:21:35.470,0:21:36.929 use. 0:21:36.929,0:21:41.399 Now in the case of I/O bus, it is a different[br]story. 0:21:41.399,0:21:52.200 First of all, we have different types of devices[br]to be connected; and second thing is that 0:21:52.200,0:21:57.720 whereas in the case of processor memory even[br]at the time of the design it is known how 0:21:57.720,0:22:03.080 much of memory it has, at the time of the[br]system installation, we do not know how many 0:22:03.080,0:22:10.330 devices we want – may be during installation[br]we would like to add a few more devices. 0:22:10.330,0:22:15.320 Generally we would find this I/O bus is in[br]contrast with the other one. 0:22:15.320,0:22:26.220 I/O bus will be a long and slow bus; slow[br]because essentially it is concerned with the 0:22:26.220,0:22:27.570 I/O part. 0:22:27.570,0:22:37.530 Generally it is lower compared with the other[br]one, which is the processor memory bus, and 0:22:37.530,0:22:44.450 it is also a long bus because you may have[br]to have many connectors for the expansion 0:22:44.450,0:22:49.870 of these devices and so on. 0:22:49.870,0:22:56.409 So we have a range of speeds to be taken care[br]of in the I/O; it is more or less standardized 0:22:56.409,0:22:58.320 in the processor memory. 0:22:58.320,0:23:03.389 The user is not directly concerned with this[br]whereas the user is very much concerned with 0:23:03.389,0:23:06.330 this. 0:23:06.330,0:23:17.610 And the third one, the back plane bus, is[br]on the PC board itself. 0:23:17.610,0:23:26.390 You have the set of signal lines connected[br]that is why it has derived the name back plane. 0:23:26.390,0:23:35.570 As I said in some systems the back plane bus[br]itself may be the processor memory bus. 0:23:35.570,0:23:45.200 So through a few system configurations we[br]will just see the essential difference between 0:23:45.200,0:23:46.300 these back plane buses. 0:23:46.300,0:23:52.201 But we take it as the back plane bus is one[br]in which you have the entire set of signal 0:23:52.201,0:24:03.340 lines on the PCB itself; so that is how it[br]got the name back plane. 0:24:03.340,0:24:12.740 Now regarding the requirements, it so happens[br]that there are two requirements for a bus 0:24:12.740,0:24:15.480 and they seem to be also conflicting. 0:24:15.480,0:24:21.580 We generally talk about bus latency. 0:24:21.580,0:24:23.700 What is the bus latency? 0:24:23.700,0:24:32.030 Whenever there is a requirement of the bus[br]for a data transfer, you would like to see 0:24:32.030,0:24:40.510 that the bus is made available as fast as[br]possible for the specific requirement. 0:24:40.510,0:24:46.399 So we would have to see that the bus latency[br]time must be minimized. 0:24:46.399,0:24:58.020 The time associated with the bus latency must[br]be minimized; that is, whenever there is a 0:24:58.020,0:25:05.839 request for the bus, the bus must be made[br]available with the least delay possible. 0:25:05.839,0:25:11.670 Then the other factor is the bus bandwidth. 0:25:11.670,0:25:23.230 This particular one conveys to us that if[br]the bandwidth is high, more data can be transferred; 0:25:23.230,0:25:30.260 that is, there is more efficient utilization. 0:25:30.260,0:25:40.649 Now more data can be transferred [br]if we can bunch all the data, buffer it and 0:25:40.649,0:25:47.420 then send it with the least amount of interaction[br]asking for address, control, things like that. 0:25:47.420,0:25:53.630 As we have seen for instance in the DMA, the[br]data is ready and available and then, like 0:25:53.630,0:25:55.190 a machine gun, it keeps going. 0:25:55.190,0:25:58.480 Every time we do not have to keep checking. 0:25:58.480,0:26:10.369 So the bus bandwidth can be increased by what[br]we say as buffering the data and transmitting 0:26:10.369,0:26:23.440 block of data so that the time that is generally[br]lost between two blocks or pieces of data 0:26:23.440,0:26:28.490 can be further minimized. 0:26:28.490,0:26:37.510 So there is buffering or storing more data[br]before the actual transmission starts. 0:26:37.510,0:26:42.179 So what we exactly gain here is that before[br]the transmission, there may be some overheads 0:26:42.179,0:26:48.830 and delay, but then there should not be any[br]delay once the transmission starts, and once 0:26:48.830,0:26:50.980 it starts, it goes very fast. 0:26:50.980,0:27:00.050 While buffering a block and transmitting blocks[br]of data, you maximize the bandwidth. 0:27:00.050,0:27:01.050 Now what happens? 0:27:01.050,0:27:06.980 When there is a block data transfer, the bus[br]is not going to be available for some other 0:27:06.980,0:27:09.669 device which requires it. 0:27:09.669,0:27:19.640 That is because when the bus is being used[br]by some other device, the one which requires 0:27:19.640,0:27:23.600 the bus is going to wait; that is the reason. 0:27:23.600,0:27:29.020 Now as we said the latency must be minimized;[br]that is, the wait period must be minimized. 0:27:29.020,0:27:36.130 We also say that the bus bandwidth must be[br]maximized. 0:27:36.130,0:27:43.230 Now while trying to maximize this, we ended[br]up buffering the data and then transmitting 0:27:43.230,0:27:51.860 the blocks of data; and while trying to maximize[br]this, we see that the latency gets affected. 0:27:51.860,0:28:00.960 That is, the device which requests the bus[br]has to wait because some other large transfer 0:28:00.960,0:28:03.129 is going on. 0:28:03.129,0:28:09.710 So these two – bus latency and bus bandwidth[br]– are actually conflicting requirements, 0:28:09.710,0:28:18.770 so there must be some compromise between these;[br]now this is very important. 0:28:18.770,0:28:27.149 Talking about different types of buses from[br]the timing point of view we talk about synchronous 0:28:27.149,0:28:36.790 buses in which the transmission takes place. 0:28:36.790,0:28:45.679 It is synchronized with some clock and of[br]course the asynchronous bus. 0:28:45.679,0:28:59.950 We have both types of buses; generally you[br]will find that when synchronous bus is used 0:28:59.950,0:29:04.869 everything must be known a priori. 0:29:04.869,0:29:15.099 For instance, in the case of processor–memory[br]interaction, the speed of the processor and 0:29:15.099,0:29:20.080 how exactly memory is organized is known,[br]whereas when it comes to I/O device we were 0:29:20.080,0:29:21.640 not sure. 0:29:21.640,0:29:29.109 We may add slow device and fast device later[br]on also; a priori we will not have everything. 0:29:29.109,0:29:35.400 So it may be better to say that it depends[br]on the individual characteristic of the device. 0:29:35.400,0:29:40.290 The bus transmission must be flexible; for[br]this asynchronous is better. 0:29:40.290,0:29:46.320 If everything is known a priori, then we can[br]make those elements in synchronous, or rather 0:29:46.320,0:29:47.849 work in synchronous. 0:29:47.849,0:29:57.879 That is, for instance, we have talked about[br]synchronous action earlier. 0:29:57.879,0:30:11.970 Remember in the initial period we are talking[br]about the states and in each state we were 0:30:11.970,0:30:14.919 saying some minimum action was going on. 0:30:14.919,0:30:21.919 The minimum action is going on and then the[br]state itself is being defined by the clock 0:30:21.919,0:30:23.859 of the system. 0:30:23.859,0:30:28.230 That is in connection with CPU, we are talking[br]about it. 0:30:28.230,0:30:38.500 Remember then we were saying in state T1 the[br]address is placed; let us say the address 0:30:38.500,0:30:41.020 line may be either 1 or 0. 0:30:41.020,0:30:50.320 So either it may be this way or it may this[br]way; actually this particular one refers to 0:30:50.320,0:30:54.510 rise time and fall time. 0:30:54.510,0:31:07.089 So in T1 the addresses is placed on the bus[br]and, let us say, in T2 the read control signal 0:31:07.089,0:31:10.810 is generated. 0:31:10.810,0:31:13.750 The read control signal is generated in T2. 0:31:13.750,0:31:19.270 The address has been placed; the read control[br]signal is generated; let us say that particular 0:31:19.270,0:31:22.880 going signal is 0 to 1. 0:31:22.880,0:31:31.890 That is, T1 address is placed; T2 wait control[br]signal is generated; on seeing read, the memory 0:31:31.890,0:31:38.889 responds with the data from the location indicated[br]by the address. 0:31:38.889,0:31:42.790 So from now from the memory side this is all[br]this from the CPU side. 0:31:42.790,0:31:51.550 Now to indicate that the memory is different[br]from these we will call these as the data 0:31:51.550,0:31:55.150 coming from the memory or memory dot data. 0:31:55.150,0:32:08.070 The data that is coming some time after the[br]memory sees the control signal read. 0:32:08.070,0:32:12.659 So let us say there is some delay. 0:32:12.659,0:32:16.820 I am just indicating the delay by this delta. 0:32:16.820,0:32:23.060 There is some delay from the time the control[br]signal is generated to the time the data is 0:32:23.060,0:32:24.540 generated. 0:32:24.540,0:32:32.960 This data actually refers to the data being[br]0. 0:32:32.960,0:32:38.960 We do not know; may be some bit is 0, some[br]bit is 1, so we would represent both. 0:32:38.960,0:32:44.409 For instance if the memory responds to the[br]8-bit data, some bits will be 1; some bits 0:32:44.409,0:32:46.770 will be 0. 0:32:46.770,0:32:51.780 Some bits may continue to be 1; some bits[br]may continue to be 0. 0:32:51.780,0:33:02.760 So when we mark this way, it basically means[br]it can be 1 or 0; this delta is the delay. 0:33:02.760,0:33:10.640 This delay is due to the memory responding[br]to the control signal read. 0:33:10.640,0:33:20.010 There can also be delay introduced by the[br]memory – that is when we talk about reading 0:33:20.010,0:33:25.030 the data; delay with reference to the address[br]also is possible. 0:33:25.030,0:33:29.379 It is not shown here; here only the particular[br]delay is shown. 0:33:29.379,0:33:41.880 Now here you can see that assuming this delta,[br]the delay, is less than one clock period, 0:33:41.880,0:33:50.120 then we say that before T3 comes, this data[br]can be read. 0:33:50.120,0:33:53.930 This indicates that the read control signal[br]in this says data is available. 0:33:53.930,0:33:58.909 That is, we may refer to this as valid data. 0:33:58.909,0:34:07.649 We say valid data because before this instant,[br]the data was not valid; during this instant, 0:34:07.649,0:34:11.050 there is some transition. 0:34:11.050,0:34:13.130 Now the valid data is available. 0:34:13.130,0:34:20.139 The CPU can actually read any time after this[br]and even before T3. 0:34:20.139,0:34:31.520 In this duration, the CPU can strobe it in,[br]but if you want to be very careful you can 0:34:31.520,0:34:38.349 see that at T3 this information is strobed,[br]meaning, let us say something like this. 0:34:38.349,0:34:46.300 For the read control this edge is used; this[br]edge is used for reading. 0:34:46.300,0:34:52.940 If that is so, we say that reading of the[br]data is synchronized with the clock. 0:34:52.940,0:35:01.940 Here this is a clear picture of synchronous[br]transmission, synchronizing with the T1 clock, 0:35:01.940,0:35:09.220 the address is generated; synchronizing with[br]T2 clock, read control is generated; and in 0:35:09.220,0:35:16.950 response to the read control, the memory places[br]the data on the bus and synchronizing with 0:35:16.950,0:35:23.010 T3, the data is read by the CPU. 0:35:23.010,0:35:30.780 So this is the synchronized transmission,[br]which means we know for sure that this delta 0:35:30.780,0:35:35.580 is not going to be more than this period. 0:35:35.580,0:35:38.960 That is, well before T3, the valid data is[br]available. 0:35:38.960,0:35:45.000 In case this is not available, we had talked[br]about the situation earlier. 0:35:45.000,0:35:52.520 In case before the next clock pulse the valid[br]data is not available, that means memory is 0:35:52.520,0:35:57.550 not responding to this control and address[br]signals. 0:35:57.550,0:36:00.130 It needs more time. 0:36:00.130,0:36:10.770 We assume this particular period is 100 nanoseconds[br]and the memory is delaying let us say by 150 0:36:10.770,0:36:12.250 nanoseconds. 0:36:12.250,0:36:16.440 That is, only 50 nanoseconds later, the valid[br]data will be available, which means well before 0:36:16.440,0:36:27.370 the next pulse, that is, T4, the data will[br]be available. 0:36:27.370,0:36:31.720 So reading cannot be performed here; so what[br]will be done? 0:36:31.720,0:36:40.070 What can be done is the read control signal[br]must be further extended beyond and taken 0:36:40.070,0:36:49.080 up to T4 because the data is not going to[br]be available here. 0:36:49.080,0:36:53.970 It is going to be available somewhere about[br]50 nanoseconds later. 0:36:53.970,0:37:07.450 So the actual valid data will be available[br]here itself; that means 1 clock pulse later, 0:37:07.450,0:37:13.040 that data can be read. 0:37:13.040,0:37:16.810 How is this achieved? 0:37:16.810,0:37:23.210 The extension of this read pulse and delaying[br]the reading is achieved as we had seen earlier. 0:37:23.210,0:37:35.200 We said that the CPU can have a ready input,[br]which can be used by the memory subsystem, 0:37:35.200,0:37:48.410 and as soon as the memory system sees the[br]read pulse, it can immediately say that the 0:37:48.410,0:37:56.790 CPU, rather memory, is not ready. 0:37:56.790,0:38:08.020 Now on seeing this ready input to the CPU,[br]on seeing that memory is not ready, then until 0:38:08.020,0:38:17.840 it becomes ready for every clock pulse, the[br]signals generated by the CPU will get extended. 0:38:17.840,0:38:26.260 At this point, when the valid data is ready,[br]that is, somewhere between T3 and T4, when 0:38:26.260,0:38:34.450 the memory is ready with the data, the memory[br]can pull this up again. 0:38:34.450,0:38:42.620 So when T4 comes, it sees that the CPU is[br]ready and reading can be performed at that 0:38:42.620,0:38:43.620 point. 0:38:43.620,0:38:45.220 So this how it is done. 0:38:45.220,0:38:48.070 We had seen this earlier. 0:38:48.070,0:38:59.430 That is, T3 is an extra state that is included[br]as a wait state; that is, the CPU was made 0:38:59.430,0:39:06.090 to wait during T3, and that was because of[br]the ready input to the CPU. 0:39:06.090,0:39:11.430 The ready input is generated by the memory. 0:39:11.430,0:39:14.941 How and why is it generated? 0:39:14.941,0:39:21.250 It is known very well that the CPU’s fast[br]memory is slow; that means a priori it is 0:39:21.250,0:39:22.470 known. 0:39:22.470,0:39:29.940 So, on seeing ready input, which is generated[br]by the CPU as output ready input to the memory, 0:39:29.940,0:39:34.820 the memory responds immediately, saying that[br]it is not going to be ready. 0:39:34.820,0:39:42.130 And how much delay is again depending on how[br]many wait states must be introduced. 0:39:42.130,0:39:50.040 Since it is known that more than one state[br]is not necessary, this will just pan for about 0:39:50.040,0:39:51.960 one state. 0:39:51.960,0:39:57.950 This is the very clear case of synchronous[br]transmission. 0:39:57.950,0:40:06.470 The CPU memory makes use of a set of signal[br]lines and the transmission is going on or 0:40:06.470,0:40:12.070 communication is going on between CPU and[br]memory in a synchronized manner; it synchronizes 0:40:12.070,0:40:15.840 with every clock edge. 0:40:15.840,0:40:23.630 In the case of I/O, we just cannot guarantee[br]that. 0:40:23.630,0:40:30.570 Some buses or devices may be fast, some devices[br]will be slow. 0:40:30.570,0:40:37.190 And it may so happen that half way through[br]the life cycle of the system, you may bring 0:40:37.190,0:40:39.080 in some new device. 0:40:39.080,0:40:47.600 We may bring in a new device, which may be[br]fast or slow. 0:40:47.600,0:40:52.770 In those situations, specifically with reference[br]to the I/O bus, it is meaningful to have an 0:40:52.770,0:41:02.740 asynchronous bus; meaning there will be a[br]signal which says starts the I/O operation 0:41:02.740,0:41:09.240 and when the I/O has finished with it, it[br]can tell that it has finished this job. 0:41:09.240,0:41:15.200 If it is a fast device, it is going to tell[br]very fast, and the CPU will note it. 0:41:15.200,0:41:23.520 If it is a slow device, the device is going[br]to take its own time and then inform. 0:41:23.520,0:41:34.450 So the master of the bus can initiate a data[br]transfer and I/O will take its own time and 0:41:34.450,0:41:39.520 then it will communicate saying when it has[br]finished the job, that is, the transfer. 0:41:39.520,0:41:49.850 In other words we can introduce what we may[br]call us some communication between master 0:41:49.850,0:42:03.190 and slave in an interlocked manner; what is[br]this communication? 0:42:03.190,0:42:10.410 The master says perform the data transfer[br]and then slave responds to it. 0:42:10.410,0:42:20.210 So in an interlocked manner you establish[br]the protocol of the communication. 0:42:20.210,0:42:30.120 That is, the master says the data is ready,[br]now you can take it; the slave says I am taking 0:42:30.120,0:42:36.130 and this it says taking it own time. 0:42:36.130,0:42:39.520 So we call this master–slave interlocked[br]communication. 0:42:39.520,0:42:47.770 It synchronizes with nothing; it will not[br]go by the clock. 0:42:47.770,0:42:52.260 It need not go by the clock; the clock can[br]very much be there. 0:42:52.260,0:43:02.940 Certainly it is not going to say that in this[br]time slot something must be done; that restricting 0:43:02.940,0:43:07.450 is not there. 0:43:07.450,0:43:13.720 We also say that a set of signals that are[br]used in the interlocked communication would 0:43:13.720,0:43:20.950 be something like the master and slave shaking[br]hands. 0:43:20.950,0:43:26.430 So we refer to these signals involved in this[br]as handshaking signals. 0:43:26.430,0:43:37.140 You may be able to appreciate why we say this. 0:43:37.140,0:43:42.640 When we meet a person, let us say we say hello. 0:43:42.640,0:43:45.710 And then, he also says hello. 0:43:45.710,0:43:48.080 Then you shake his hands and say how do you[br]do. 0:43:48.080,0:43:49.980 And he also says how do you do. 0:43:49.980,0:43:53.450 It is somewhat like that: the master says[br]hello, are you there? 0:43:53.450,0:43:56.850 The slave says, yes I am here. 0:43:56.850,0:44:03.350 Then the master says here is the data; the[br]slave says I have taken the data. 0:44:03.350,0:44:08.830 That means a set of signals involved in this[br]process are referred to as handshaking signals; 0:44:08.830,0:44:17.700 they see to it that the communication goes[br]in an orderly manner, and for a person who 0:44:17.700,0:44:25.080 is not used to speaking very fast, takes his[br]own time and then responds with the hello 0:44:25.080,0:44:28.350 or how do you do, it may be fast; some may[br]be slow. 0:44:28.350,0:44:36.240 The same situation exists here too; in other[br]words what we need is a few extra signals, 0:44:36.240,0:44:37.960 somewhat like this. 0:44:37.960,0:44:42.260 The master may place the address – let us[br]just take a read cycle itself – the master 0:44:42.260,0:44:50.141 may place the address and then it may generate[br]another signal, which says that the address 0:44:50.141,0:45:03.320 is placed and that signal will be sensed by[br]the slave and it will respond saying I was 0:45:03.320,0:45:07.500 sensed there, and it will take the address. 0:45:07.500,0:45:21.070 Then the master will generate a read signal;[br]and then the slave knows that from the address, 0:45:21.070,0:45:25.810 the slave must read and place the data. 0:45:25.810,0:45:31.380 After it places the data, it says now the[br]data is ready. 0:45:31.380,0:45:39.360 The master will respond saying it will take[br]the valid data that is available on the bus; 0:45:39.360,0:45:43.810 some extra signals are introduced. 0:45:43.810,0:45:58.140 So in this way, the address is placed; I will[br]avoid this bipolar signal; I will just using 0:45:58.140,0:46:02.410 only one, just to show you the sequence. 0:46:02.410,0:46:04.640 Let us say it is something like this. 0:46:04.640,0:46:11.650 The address is placed; I am just assuming[br]only one this thing at some time edge. 0:46:11.650,0:46:21.790 Since we have assumed read cycle, let us say[br]that after the address is placed, the read 0:46:21.790,0:46:30.040 signal is [br]also introduced. 0:46:30.040,0:46:34.820 Now there are different ways in which we can[br]use a handshake signal; I am just assuming 0:46:34.820,0:46:37.430 one specific sequence. 0:46:37.430,0:46:40.920 So the address is placed and read is indicated. 0:46:40.920,0:46:50.630 From the master point of view, it can indicate[br]that it wants the slave to respond by reading 0:46:50.630,0:46:54.800 the contents of the location, the address[br]of which is given. 0:46:54.800,0:47:03.300 So after it has performed its job, the master[br]indicates through one hand shake signal; we 0:47:03.300,0:47:07.610 will call it MSYNC. 0:47:07.610,0:47:20.300 This in fact is an indication [br]that it wants reading to be performed by the 0:47:20.300,0:47:29.280 slave and it also gives indication of the[br]address. 0:47:29.280,0:47:46.380 On seeing the MSYNC signal, the slave understands[br]all this, and in response to this, the slave 0:47:46.380,0:47:53.980 can respond with the data, that is, the memory. 0:47:53.980,0:47:59.850 We assume this is memory response data. 0:47:59.850,0:48:07.460 Whatever may be the delay that delay is because[br]of the memory? 0:48:07.460,0:48:20.220 After that delay, it generates the data and[br]this is now available on the bus – valid 0:48:20.220,0:48:23.840 data. 0:48:23.840,0:48:29.150 Let us create some space for the other thing. 0:48:29.150,0:48:40.880 After the data is placed, in this case the[br]memory can generate a similar slave SYNC signal 0:48:40.880,0:48:51.840 and indicate that after the instant, it will[br]indicate that 0:48:51.840,0:48:54.600 from the point of view of slave, it has done[br]its job. 0:48:54.600,0:49:05.140 The master is indicated by placing address[br]and read: it is an indication to the slave 0:49:05.140,0:49:09.200 that the slave must perform read. 0:49:09.200,0:49:20.030 On seeing this master SYNC, the slave has[br]responded by generating the data and placing 0:49:20.030,0:49:22.310 it on the bus. 0:49:22.310,0:49:26.950 After it has done its job, the slave is indicating. 0:49:26.950,0:49:34.730 Now this SSYNC is the signal given or generated[br]by the slave. 0:49:34.730,0:49:39.960 On seeing this SSYNC signal, the master knows[br]that whatever it wants is available on the 0:49:39.960,0:49:48.480 bus because after this instant, that is, on[br]seeing the SSYNC signal, the master knows 0:49:48.480,0:49:54.340 that the required information is available. 0:49:54.340,0:50:01.960 Now the master, on seeing this, will read;[br]that means, this read signal will continue 0:50:01.960,0:50:08.670 certainly beyond this for some time; after[br]that it will terminate. 0:50:08.670,0:50:20.000 That means by this time the master has read[br]the data, then after it has read the data 0:50:20.000,0:50:27.220 the master may terminate its signal, that[br]is, after this instant when the data has been 0:50:27.220,0:50:39.300 read, the master will terminate its signal[br]and on seeing this, the slave may respond 0:50:39.300,0:50:42.250 with a few things. 0:50:42.250,0:50:53.150 Suddenly on seeing this MSYNC going negative,[br]the SSYNC also will be pulled down by the 0:50:53.150,0:50:56.510 slave. 0:50:56.510,0:51:05.560 This is the indication that the slave knows[br]that the master has performed its job of reading, 0:51:05.560,0:51:08.630 now it is closing the whole show. 0:51:08.630,0:51:16.970 So we say that there are two hand shake signals,[br]one MSYNC asserted by the master is an indication 0:51:16.970,0:51:27.400 to the slave that it wants something to be[br]done and on doing that particular work, the 0:51:27.400,0:51:38.780 slave asserts the signal and on seeing the[br]assertion of SSYNC, MSYNC, the master, concludes 0:51:38.780,0:51:50.500 its job of reading and then negates the MSYNC[br]and on seeing the negation of MSYNC, the slave 0:51:50.500,0:51:52.690 also negates it. 0:51:52.690,0:52:01.230 So we see that the signals are asserted, that[br]means the signals are placed and the signals 0:52:01.230,0:52:10.670 are negated; that is the signals are removed[br]and you can see the specific sequence. 0:52:10.670,0:52:17.230 Now there is absolutely no clock that need[br]be used here. 0:52:17.230,0:52:21.550 On seeing the signal, the other signal is[br]generated; on seeing the negation of this 0:52:21.550,0:52:28.970 signal, the other signal is generated; and[br]in between, the required activity is done. 0:52:28.970,0:52:36.040 This is the way the ASYNC bus will work and[br]you need a set of extra signals for this. 0:52:36.040,0:52:45.250 These extra signals are something like a clock[br]because they really do the timing, but it 0:52:45.250,0:52:50.160 is not strict clock periods like this. 0:52:50.160,0:52:56.650 So generally these are timing signals; that[br]is about the synchronization. 0:52:56.650,0:53:54.990 We will see more about these processes in[br]the next lecture.